1. Field of the Invention
The present invention pertains to a system, a method, and a program for making it possible to generate a circuit based on behavioral-level description information in which information on the circuit is described at a behavioral level, particularly to the system, the method, and the program for making it possible to automatically generate a power control circuit.
2. Description of the Related Art
Recently, with rapid progress in semiconductor process technology, a scale of circuit design has been enlarged, and the circuit has become complicated. This causes two serious problems as described below.
One of the problems is a problem on productivity of the design.
There is a large difference between a design scale of a circuit required of a designer within a predetermined design period and a design scale of a circuit which the designer can actually design within the predetermined design period, and the difference has been increasing year by year.
However, the above problem on the design productivity has long been present, and solved by an EDA (Electronic Design Automation) tool each time the problem became prominent.
An automatic place-and-route tool utilized in the late 1970s and a logic synthesis tool utilized in the late 1980s to the early 1990s can be cited as examples of the EDA tool.
Currently a better EDA tool is desired because the problem on the design productivity has become prominent again. Therefore, recently a behavioral synthesis tool attracts attention as the EDA tool.
The behavioral synthesis tool generates circuit description information (RT-level circuit information) at a register transfer level (RT-level) from circuit description information at a behavioral level.
In the behavioral synthesis tool, because the circuit is described at the behavioral level, the same function can be expressed by lesser description. Additionally, the behavioral synthesis tool can make verification at the behavioral level at a speed higher than that of the RT-level circuit.
Therefore, the behavioral synthesis tool has been used in the late 1990s.
The second problem is a problem on power consumption.
An electric power consumed in the circuitry tends to increase by improvement of an integration degree of circuits.
Although, until now, the reduction in dynamic power consumption consumed in operating a circuit has been the most important problem, recently the reduction in static power consumption caused by a leak current and the like also becomes important with an advancement in microfabrication technique.
Therefore, there is disclosed a low power consumption design technology concerning clock gating and power gating (for example, see Shinichiro Mutoh, et al., “Design Method of MTCMOS Power Switch for Low-Voltage High-Speed LSIs,” ASP-DAC, 1999).
There is also disclosed MT (Multi Threshold)-CMOS (for example, see Shinichiro Mutoh, et al., “1-V Power Supply High-Speed Digital Circuit Technology with Multithreshold Voltage CMOS,” IEEE JSSC, vol. 30, no. 8, pp 847-854, August 1995).
There is also disclosed VT (Variable Threshold)-CMOS (for example, see Tadahiro Kuroda, et al., “A 0.9V, 150-MHz, 10-mW, 4 mm2, 2-D Discrete Cosine Transform Core Processor with Variable Threshold-Voltage (VT) Scheme,” IEEE JSSC, vol. 31, no. 11, pp. 1770-1779, November 1996).
There is disclosed a technique of generating circuit description in which clock gating is automatically given when a circuit described by a high-level language is synthesized at high level and converted into description of RTL (for example, see Japanese Patent Application Laid-Open No. 2006-155533).
There is disclosed a technique of functioning as a circuit design support device which can easily recognize a correlation of design information between design processes (for example, see Japanese Patent Application Laid-Open No. 2006-139624).
There is disclosed a technique where a loop processing in a control data flow graph (CDFG) is pipelined with a small increased area in behavioral synthesis in which hardware is synthesized from the operation description (for example, see Japanese Patent Application Laid-Open No. 2004-326463).
There is disclosed a technique of generating a low power consumption circuit in which the wasted electric power is decreased (for example, see Japanese Patent Application Laid-Open No. 2002-366596).
However, when the above conventionally proposed low power consumption design technologies are applied to the RT-level circuit, it is necessary to manually perform the design including the power control circuit. Therefore, a long design period or a verification period is required because a defect is probably mixed in the design. Accordingly, there is a demand for a technique for making it possible to automatically generate the power control circuit.
Although the technique of automatically generating the power control circuit is disclosed in Japanese Patent Application Laid-Open Nos. 2006-155533, 2006-139624, 2004-326463, and 2002-366596, there is no description in which the power control circuit is automatically generated by utilizing the detailed information on the component constituting the circuit.